1. Field of the Invention
This invention relates to a semiconductor integrated circuit device of multilayer interconnection structure.
2. Description of the Related Art
In recent large scale semiconductor integrated circuit devices (LSI), the integration density of elements has become extremely high, and the current consumption has increased accordingly. In order to supply a power source voltage to an LSI requiring such a large current capacity, one conventional method used to attain the current capacity required is to employ a plurality of power source pads. However, using this conventional method, it is necessary to provide a large number of external terminals (pins) on the LSI. Moreover, the above method is not suitable for use with an LSI through which a large number of input and output signals pass. In addition, the greater the number of pins required, the greater the size of the chip will be.
Therefore, in the prior art, another method of increasing the current capacity has been developed, in which a plurality of lead-out wirings extend from the power source pad or the wiring width of the lead-out wiring is increased. FIG. 1 is a plan view of a conventional LSI chip the current capacity of which is increased by use of the above described methods. In FIG. 1, 10 denotes the main body of the chip, and 11, an internal circuit area is provided therein. Power source interconnection layers 12 and 13 formed of metal are arranged in annular form around internal circuit area 11 or on the peripheral portion of the chip, and supply high potential power source voltage Vcc and low potential power source voltage Vss to circuit area 11. In FIG. 1, 14 denotes a power source pad to which power source voltage Vcc to be supplied to power source interconnection layer 12 is supplied from outside the chip, power source pad 14 being connected to an external pin of the LSI, via a bonding wire (not shown), as well as to power source interconnection layer 12, via lead-out interconnection layer 15. 16 and 17 denote power source pads to which power source voltage Vss to be supplied to power source interconnection layer 13 is supplied from outside the chip, pads 16 and 17 being connected to external pins, via bonding wires (not shown). Power source pad 16 is additionally connected to power source interconnection layer 13, via lead-out interconnection layer 18, power source pad 17 being also connected to power source interconnection layer 13, via three lead-out interconnection layers 19, 20 and 21. Althrough not shown, various pads for other power source supply and for signal input and output are arranged on the peripheral portion of main chip body 10. The entire chip is basically covered with a protection film (not shown), and openings are formed in those portions of the protection film at which each of the pads for connection with the bonding wires are provided.
In the case where the current capacity is increased by increasing the widths of lead-out interconnection layers 15 and 18 extending from pads such as power source pads 14 and 16, the condition of bonding the bonding wire to the pad must be taken into consideration as the limiting factor, and therefore the width of the interconnection layer 18 cannot be made too large. The limiting factor is that the pad shape must be correctly recognized in the bonding process. That is, it is definitely necessary that the pad area must be clearly recognized. Therefore, it is basically necessary to set the width of the lead-out interconnection layer to be smaller than that of the pad. If it is required to set the width of the lead-out interconnection layer to be equal to or larger than that of the pad, it is necessary to form pad recognition slits 22 in lead-out interconnection layers 15 and 18 as shown in FIG. 1. Thus, even if the width of the lead-out interconnection layer is increased, the pad shape can be correctly recognized at the time of bonding by forming the slits. However, formation of the slits will increase the chip size. This is because the limiting factor is also involved in the case of the bonding with respect to the pad.
FIG. 2 is a pattern plan view showing an enlarged portion of the chip shown in FIG. 1. In FIG. 2, 23 denotes input/output cells formed on the peripheral portion of main chip body 10, 13 denotes a power source interconnection layer for supplying power source voltage Vss to input/output cells 23, and 24 denotes an opening of power source pad 16, in which no protection film is formed and a bonding wire is connected to the pad. The limiting factor involved in this chip is that distance 1 between the end of lead-out interconnection layer 18 connected to pad 16 and opening 26 formed in an insulation film in another pad 25 must be set to be larger than a predetermined value. Distance 1 is necessary to protect elements from being destroyed by mechanical shock at the time of bonding, short-circuiting caused by bonding effected with low precision, or the like. Thus, it is necessary to set the distance pads to be larger than a predetermined value. In that way, when the width of the lead-out interconnection layer is increased, the chip size will be increased.
In a case where, the pad as shown in, for example, in FIG. 1, is connected to the power source interconnection layer via a plurality of lead-out interconnection layers, and can serve a current capacity of a plurality of pads by itself, there is required an increase in area and hence an increase in chip size. Thus, in order to increase the power source current capacity according to the conventional method, the chip size must be increased.